1. Technical Field
Various embodiments of the present invention relate to semiconductor memory apparatuses and related methods. In particular, certain embodiments relate to a precharge signal generation circuit of a semiconductor memory apparatus.
2. Related Art
FIG. 1 is a block diagram of a typical precharge signal generation circuit. As illustrated in FIG. 1, a precharge signal generation circuit 1 of a semiconductor memory apparatus may include a precharge signal generation unit 2 and a decoder 3.
The precharge signal generation unit 2 may include a first shift block 10, a second shift block 20, a third shift block 30, and a fourth shift block 40.
The first shift block 10 generates read/write precharge commands APCGCMD_RD and APCGCMD_WT in response to a precharge command APCG_CMD, a clock signal ICLK, a write flag signal WT_STATE, and control signals TWRX<2:3> and TWR_C<1:4>.
The write flag signal WT_STATE is at a high level in a writing operation and at a low level in a read operation.
The second shift block 20 generates bank precharge addresses APCGBK_WT<0> and APCGBK_RD<0> in response to a bank column address strobe signal CBK<0>, the clock signal ICLK, the write flag signal WT_STATE, and the control signals TWRX<2:3> and TWR_C<1:4>.
The third shift block 30 generates bank precharge addresses APCGBK_WT<1> and APCGBK_RD<1> in response to a bank column address strobe signal CBK<1>, the clock signal ICLK, the write flag signal WT_STATE, and the control signals TWRX<2:3> and TWR_C<1:4>.
The fourth shift block 40 generates bank precharge addresses APCGBK_WT<2> and APCGBK_RD<2> in response to a bank column address strobe signal CBK<2>, the clock signal ICLK, the write flag signal WT_STATE, and the control signals TWRX<2:3> and TWR_C<1:4>.
The decoder 3 generates precharge signals APCG<0:7> in response to the read/write precharge commands APCGCMD_RD and APCGCMD_WT and the read/write bank precharge addresses APCGBK_RD<0:2> and APCGBK_WT<0:2>.
FIG. 2 is a circuit diagram of the first shift block illustrated in FIG. 1. As illustrated in FIG. 2, the first shift block 10 may include a plurality of flip-flops DFFs, a plurality of control flip-flops DFFCs, a plurality of inverters IV1 to IV5, a plurality of AND gates AND1 to AND4, and a plurality of pass gates PG1 to PG4.
The second shift block 20, the third shift block 30, and the fourth shift block 40 may have the same configuration as that of the first shift block 10.
According to the operational specifications of a semiconductor memory apparatus, the write precharge command APCGCMD_WT and the bank precharge addresses APCGBK_WT<0:2> need to be generated by delaying the precharge command APCG_CMD by a write-related precharge standard time, that is, tWR (last data-in to precharge). The read precharge command APCGCMD_RD and the bank precharge addresses APCGBK_RD<0:2> need to be generated by delaying the bank column address strobe signals CBK<0:2> by a read-related precharge standard time, that is, 4tCK (ICLK of four cycles).
The first shift block 10, the second shift block 20, the third shift block 30, and the fourth shift block 40 are designed according to the truth table illustrated in FIG. 2 in order to satisfy the above-described conditions.
For example, it is assumed that the precharge command APCG_CMD, that is, a read with precharge command RD with auto-precharge is input.
At this time, since a read operation is performed, the write flag signal WT_STATE is at a low level.
Thus, the precharge command APCG_CMD is delayed by 4tCK through four flip-flops DFFs, so that the read precharge command APCGCMD_RD is activated to a high level through the AND gate AND1.
Since the write flag signal WT_STATE is at the low level, the output of the AND gate AND4 is locked to a low level. That is, the write precharge command APCGCMD_WT is deactivated.
Meanwhile, it is assumed that tWR is set to 5 and the precharge command APCG_CMD, that is, a write precharge command WT with auto-precharge is input.
At this time, since a write operation is performed, the write flag signal WT_STATE is at a high level.
Since the write flag signal WT_STATE is at the high level, the output of the AND gate AND1 is locked to a low level. That is, the read precharge command APCGCMD_RD is deactivated to a low level.
When tWR is 5, in the truth table, the control signal TWR_C<1> of the control signals TWRX<2:3> and TWR_C<1:4> has a logic value of ‘1’ (high level), the other control signals have a logic value of ‘0’ (low level), and the write flag signal WT_STATE is at the high level.
Since the control signals TWRX<2:3> are at a low level, the AND gates AND2 and AND3 output a low level.
Thus, the operations of the flip-flop DFF and the control flip-flop DFFC, which receive the outputs of the AND gates AND2 and AND3 through clock terminals thereof, are stopped.
The control flip-flops DFFCs receiving the control signal TWRX<2> select a signal WT_APCG obtained by delaying the precharge command APCG_CMD by 4tCK through the four flip-flop DFFs.
The control flip-flops DFFCs receiving the control signal TWRX<2> and the flip-flop DFFs connected to the control flip-flops DFFCs output signals WR<5:8> by delaying the signal WT_APCG by 1tCK in response to the clock signal ICLK.
Since the logic value of control signal TWR_C<1> is a high level, the signal WR<5> is selected from the signals WR<5:8>. Furthermore, since the write flag signal WT_STATE is at the high level, the write precharge command APCGCMD_WT is activated to a high level through the AND gate AND4.
As a consequence, the precharge command APCG_CMD is delayed by 5tCK and is output as the write precharge command APCGCMD_WT.
However, in the semiconductor apparatus described above, the plurality of circuit blocks such as the first shift block 10, the second shift block 20, the third shift block 30, and the fourth shift block 40 take a substantial amount of circuit area. Furthermore, since each circuit block requires the clock signal ICLK, the load of the clock signal ICLK increases, so that the size of a driver for the clock signal ICLK also increases, resulting in an increase in current consumption.